Dynamic Random Access Memory utilizes capacitors to store bits of information within an integrated circuit. A capacitor is formed by placing a dielectric material between two electrodes formed from conductive materials. A capacitor's ability to hold electrical charge (i.e., capacitance) is a function of the surface area of the capacitor plates A, the distance between the capacitor plates d (i.e. the physical thickness of the dielectric layer), and the relative dielectric constant or k-value of the dielectric material. The capacitance is given by:
                    C        =                  κ          ⁢                                          ⁢                      ɛ            o                    ⁢                      A            d                                              (                  Eqn          .                                          ⁢          1                )            where ∈0 represents the vacuum permittivity.
The dielectric constant is a measure of a material's polarizability. Therefore, the higher the dielectric constant of a material, the more charge the capacitor can hold. Therefore, if the k-value of the dielectric is increased, the area of the capacitor can be decreased and maintain the desired cell capacitance. Reducing the size of capacitors within the device is important for the miniaturization of integrated circuits. This allows the packing of millions (mega-bit (Mb)) or billions (giga-bit (Gb)) of memory cells into a single semiconductor device. The goal is to maintain a large cell capacitance (generally ˜10 to 25 fF) and a low leakage current (generally <10−7 A cm−2). The physical thickness of the dielectric layers in DRAM capacitors could not be reduced unlimitedly in order to avoid leakage current caused by tunneling mechanisms which exponentially increases as the thickness of the dielectric layer decreases.
Traditionally, SiO2 has been used as the dielectric material and semiconducting materials (semiconductor-insulator-semiconductor [SIS] cell designs) have been used as the electrodes. The cell capacitance was maintained by increasing the area of the capacitor using very complex capacitor morphologies while also decreasing the thickness of the SiO2 dielectric layer. Increases of the leakage current above the desired specifications have demanded the development of new capacitor geometries, new electrode materials, and new dielectric materials. Cell designs have migrated to metal-insulator-semiconductor (MIS) and now to metal-insulator-metal (MIM) cell designs for higher performance.
One class of high-k dielectric materials possessing the characteristics required for implementation in advanced DRAM capacitors are high-k metal oxide materials. Examples of suitable dielectric materials comprise SiO2, a bilayer of SiO2 and SixNy, SiON, Al2O3, HfO2, HfSiOx, ZrO2, Ta2O5, TiO2, Nb2O5, SrTiO3 (STO), BaSrTiOx (BST), PbZrTiOx (PZT), etc. TiO2 and ZrO2 are two specific examples of metal oxide dielectric materials which display significant promise in terms of serving as a high-k dielectric material for implementation in DRAM capacitors.
Typically, DRAM devices at technology nodes of 80 nm and below use MIM capacitors wherein the electrode materials are metals. These electrode materials generally have higher conductivities than the semiconductor electrode materials, higher work functions, exhibit improved stability over the semiconductor electrode materials, and exhibit reduced depletion effects. The electrode materials must have high conductivity to ensure fast device speeds. Representative examples of electrode materials for MIM capacitors are metals, conductive metal oxides, conductive metal silicides, conductive metal nitrides (i.e. TiN), or combinations thereof. MIM capacitors in these DRAM applications utilize insulating materials having a dielectric constant, or k-value, significantly higher than that of SiO2 (k=3.9). For DRAM capacitors, the goal is to utilize dielectric materials with k values greater than about 40. Such materials are generally classified as high-k materials. Representative examples of high-k materials for MIM capacitors are non-conducting metal oxides, non-conducting metal nitrides, non-conducting metal silicates or combinations thereof. These dielectrics may also include additional dopant materials.
A figure of merit in DRAM technology is the electrical performance of the dielectric material as compared to SiO2 known as the Equivalent Oxide Thickness (EOT). A high-k material's EOT is calculated using a normalized measure of silicon dioxide (SiO2 k=3.9) as a reference, given by:
                    EOT        =                              3.9            κ                    ·          d                                    (                  Eqn          .                                          ⁢          2                )            where d represents the physical thickness of the capacitor dielectric.
As DRAM technologies scale below the 40 nm technology node, manufacturers must reduce the EOT of the high-k dielectric films in MIM capacitors in order to increase charge storage capacity. The goal is to utilize dielectric materials that exhibit an EOT of less than about 0.8 nm while maintaining a physical thickness of about 5-20 nm.
Generally, as the dielectric constant of a material increases, the band gap of the material decreases. For example. The rutile phase of TiO2 has a k-value of about 80 and a band gap of about 3.0 eV while ZrO2 in the tetragonal phase has a k-value of about 43 and a band gap of about 5.8 eV. The low band gap may lead to high leakage current in the device. As a result, without the utilization of countervailing measures, capacitor stacks implementing high-k dielectric materials may experience large leakage currents. High work function electrodes (e.g., electrodes having a work function of greater than 5.0 eV) may be utilized in order to counter the effects of implementing a reduced band gap high-k dielectric layer within the DRAM capacitor. Metals, such as platinum, gold, ruthenium, and ruthenium oxide are examples of high work function electrode materials suitable for inhibiting device leakage in a DRAM capacitor having a high-k dielectric layer. The noble metal systems, however, are prohibitively expensive when employed in a mass production context. Moreover, electrodes fabricated from noble metals often suffer from poor manufacturing qualities, such as surface roughness, poor adhesion, and form a contamination risk in the fab.
Leakage current in capacitor dielectric materials can be due to Schottky emission, Frenkel-Poole defects (e.g. oxygen vacancies (Vox) or grain boundaries), or Fowler-Nordheim tunneling. Schottky emission, also called thermionic emission, is a common mechanism and is the thermally activated flow of charge over an energy barrier whereby the effective barrier height of a MIM capacitor controls leakage current. The nominal barrier height is a function of the difference between the work function of the electrode and the electron affinity of the dielectric. The electron affinity of a dielectric is closely related to the conduction band offset of the dielectric. The Schottky emission behavior of a dielectric layer is generally determined by the properties of the dielectric/electrode interface. Frenkel-Poole emission allows the conduction of charges through a dielectric layer through the interaction with defect sites such as vacancies, grain boundaries, and the like. As such, the Frenkel-Poole emission behavior of a dielectric layer is generally determined by the dielectric layer's bulk properties. Fowler-Nordheim emission allows the conduction of charges through a dielectric layer through direct tunneling without any intermediary interaction with e.g. defects. As such, the Fowler-Nordheim emission behavior of a dielectric layer is generally determined by the physical thickness of the dielectric layer. This leakage current is a primary driving force in the adoption of high-k dielectric materials. The use of high-k materials allows the physical thickness of the dielectric layer to be as thick as possible while maintaining the required capacitance (see Eqn 1 above).
Conductive metal oxides, conductive metal silicides, conductive metal nitrides, or combinations thereof comprise other classes of materials that may be suitable as DRAM capacitor electrodes. Generally, transition metals and their conductive binary compounds form good candidates as electrode materials. The transition metals exist in several oxidation states. Therefore, a wide variety of compounds are possible. Different compounds may have different crystal structures, electrical properties, etc. It is important to utilize the proper compound for the desired application.
The use of crystalline conductive metal oxides as a second electrode in MIM DRAM capacitors has been difficult due to a number of problems. After the formation of the second electrode, the capacitor stack is then subjected to a post metallization anneal (PMA) treatment. The PMA treatment serves to crystallize the second electrode and to anneal defects and interface states that are formed at the dielectric/second electrode interface during the deposition. Also, if there is no post dielectric anneal (PDA) treatment done before metallization, the PMA treatment can served to crystallize the dielectric layer. Examples of the PDA and PMA treatments are further described in U.S. application Ser. No. 13/159,842 filed on Jun. 14, 2011, entitled “METHOD OF PROCESSING MIM CAPACITORS TO REDUCE LEAKAGE CURRENT” and is incorporated herein by reference. Conductive metal oxides are sensitive to oxidation to oxygen-rich compounds that negatively impact their performance as an electrode material. Reducing atmosphere anneal processes are not an option at this stage of the device manufacture because they would degrade the performance of the dielectric layer through the formation of oxygen vacancies.
Additionally, DRAM capacitor stacks may undergo various refinement process steps after fabrication. These refinement processes may include post-fabrication chemical and thermal processing (i.e., oxidation or reduction). For instance, after initial DRAM capacitor stack fabrication, a number of high temperature (up to about 600 C) processes may be applied to complete the device fabrication. Typically, the second electrode layer as well as several of the other capacitor stack layers may be patterned using well known photolithography and etch steps. The purpose of this step is to generate the final 3-dimensional structure of the capacitor. However, it has been found that the patterning of the capacitor stack may damage the materials leading to high leakage current. Therefore, process steps must be developed to complete the integration of the capacitor stack into the final DRAM device manufacturing process sequence. The etch steps may be wet-chemical based or may be reactive ion-based. During these subsequent process steps, the DRAM electrode materials must remain chemically, physically, and structurally stable. They must maintain the structural, compositional, physical, and electrical properties that have been developed. Furthermore, they should not undergo significant interaction or reaction with the dielectric layer which may degrade the performance of the DRAM capacitor. Therefore, there is a need for methods that address the requirements listed above and allow the use of conductive metal oxide materials as a second electrode in the manufacture of DRAM MIM capacitors.